In an effort to reduce the size of mobile electronic devices and increase the battery life of such devices, an emphasis has been placed on implementing low voltage circuit designs. However, designers of low voltage circuits face many challenges. One such challenge includes the design of reliable low voltage memory circuits. In particular, current static random access memory (SRAM) cell designs can suffer serious performance degradation at lower supply voltages. Operating parameters, such as signal to noise margin (SNM) during the read phase, write margin (WM) during the write phase, and cell current (Icell) during both the read and the write phase should be maintained within certain limits to ensure robust memory system operation. These parameters typically degrade below acceptable levels when the supply voltage for the cell is lowered to meet new design standards. Accordingly, there is a need for a device and method that provides improved operational parameters for SRAM memory cells at low voltages.